This invention relates generally to RFID systems and more specifically to an RFID system that incorporates at least one RFID receiver system and a distributed exciter architecture that defines a plurality of interrogation spaces.
The detection of signals in difficult environments, such as where the signal to noise ratio is very low and/or the interference from other signals is very high, has always been a challenging problem.
In RFID systems such as the RFID systems described in U.S. patent application Ser. No. 11/971,678, entitled “RFID System with Low Complexity Implementation and Pallet Coding Error Correction,” filed Jan. 9, 2008, the disclosure of which is incorporated by reference herein in its entirety, RFID receiver subsystems rely on an enhanced RF front end as well as processing capabilities, for detecting very low power signals in the presence of additive white Gaussian noise with further channel distortions in in-door or out-door wireless propagation channels. These techniques are particularly applicable to Radio Frequency Identification (RFID) based systems. FIG. 12 illustrates a transmit and receive RFID reader similar to the transmit and receive readers described in U.S. patent application Ser. No. 11/971,678 and the specifics of the RF front end. The reader (12-9) follows an RFID tag protocol to communicate with tags (12-5) using the same transmit and receive frequencies. The time-line showing this communication is shown in FIG. 13. The protocol governs the reader transmission of (12-4) data (13-2) and a continuous waveform (CW) (13-4) to the tag, and reception (12-2) of the tag's data (13-10). From FIG. 13, during the period that the tag is backscattering a packet to the reader, the reader is transmitting CW signal (13-4). That is the received signal is a composite of transmitted CW and received tag signal (12-7). The receiver subsystem (12-9) performs baseband down conversion (12-12, 12-14), filtering (12-16, 12-18), and amplification (12-20, 12-22). At the output of the baseband amplifiers the signal from the tag is present, as well as a strong DC component. This DC component is canceled by using DC block capacitors (12-27, 12-29). To further improve the performance of the DC cancellation, the input to the DC block capacitors (12-27, 12-29) is controlled through a switch (12-24, 12-26) which is only closed during the period that the system is receiving data from the tag, as depicted in FIG. 13 (13-10). The digital processor (12-46), which maintains the system timing control of the switch control, opens the switch during the reader transmit periods (13-2, 13-6, 13-14, 13-18), and closes the switches during the expected receive periods (13-4, 13-10, 13-16). The output of the DC cancellation capacitors is followed by the AGC loops (12-32, 12-34), analog to digital converters (12-36, 12-38), and digital processor (12-40), which includes the control algorithms.